{"id":4004,"date":"2025-09-18T11:12:00","date_gmt":"2025-09-18T11:12:00","guid":{"rendered":"https:\/\/lp.szlogic.cn\/glossary\/what-is-pcl-express-pcie\/"},"modified":"2026-06-10T01:17:04","modified_gmt":"2026-06-10T01:17:04","slug":"what-is-pcl-express-pcie","status":"publish","type":"post","link":"https:\/\/resourceslp.szlogic.cn\/vi\/glossary\/what-is-pcl-express-pcie","title":{"rendered":"PCI Express (PCIe) L\u00e0 G\u00ec? \u0110\u1ecbnh Ngh\u0129a, C\u00e1c Phi\u00ean B\u1ea3n v\u00e0 \u1ee8ng D\u1ee5ng"},"content":{"rendered":"

\u27a3 <\/strong>PCI Express (PCIe) L\u00e0 G\u00ec?<\/h2>\n\n\n\n

PCI Express (Giao di\u1ec7n K\u1ebft n\u1ed1i Th\u00e0nh ph\u1ea7n Ngo\u1ea1i vi Nhanh, PCIe)<\/strong> l\u00e0 m\u1ed9t ti\u00eau chu\u1ea9n giao di\u1ec7n t\u1ed1c \u0111\u1ed9 cao k\u1ebft n\u1ed1i c\u00e1c th\u00e0nh ph\u1ea7n ph\u1ea7n c\u1ee9ng quan tr\u1ecdng\u2014nh\u01b0 card \u0111\u1ed3 h\u1ecda, \u1ed5 SSD v\u00e0 b\u1ed9 \u0111i\u1ec1u h\u1ee3p m\u1ea1ng\u2014v\u1edbi bo m\u1ea1ch ch\u1ee7 c\u1ee7a m\u00e1y t\u00ednh. N\u00f3 thay th\u1ebf c\u00e1c ti\u00eau chu\u1ea9n PCI v\u00e0 PCI-X c\u0169 h\u01a1n b\u1eb1ng m\u1ed9t ki\u1ebfn tr\u00fac n\u1ed1i ti\u1ebfp, \u0111i\u1ec3m-\u0111i\u1ec3m<\/strong>, mang l\u1ea1i b\u0103ng th\u00f4ng cao h\u01a1n v\u00e0 \u0111\u1ed9 tr\u1ec5 th\u1ea5p h\u01a1n.<\/p>\n\n\n\n

M\u1ed7i thi\u1ebft b\u1ecb PCIe giao ti\u1ebfp v\u1edbi h\u1ec7 th\u1ed1ng th\u00f4ng qua c\u00e1c \u0111\u01b0\u1eddng d\u1eabn (lanes)<\/strong>chuy\u00ean d\u1ee5ng\u2014t\u1eebng c\u1eb7p t\u00edn hi\u1ec7u truy\u1ec1n v\u00e0 nh\u1eadn. M\u1ed9t \u0111\u01b0\u1eddng d\u1eabn \u0111\u01a1n \u0111\u01b0\u1ee3c k\u00fd hi\u1ec7u l\u00e0 x1<\/strong>, trong khi c\u00e1c k\u1ebft n\u1ed1i r\u1ed9ng h\u01a1n t\u0103ng d\u1ea7n l\u00ean m\u1ee9c x4, x8, x16 ho\u1eb7c x32<\/strong>, cung c\u1ea5p th\u00f4ng l\u01b0\u1ee3ng t\u01b0\u01a1ng \u1ee9ng cao h\u01a1n. Thi\u1ebft k\u1ebf linh ho\u1ea1t n\u00e0y cho ph\u00e9p PCIe v\u1eadn h\u00e0nh m\u1ecdi th\u1ee9, t\u1eeb c\u00e1c card m\u1edf r\u1ed9ng c\u1ea5p nh\u1eadp m\u00f4n \u0111\u1ebfn GPU v\u00e0 gi\u1ea3i ph\u00e1p l\u01b0u tr\u1eef hi\u1ec7u n\u0103ng cao.<\/p>\n\n\n\n

\"What<\/figure>\n\n\n\n

\u27a3 <\/strong>C\u00e1c Th\u1ebf H\u1ec7 PCIe v\u00e0 B\u0103ng Th\u00f4ng<\/h2>\n\n\n\n

M\u1ed9t trong nh\u1eefng kh\u00eda c\u1ea1nh quan tr\u1ecdng nh\u1ea5t c\u1ee7a PCIe l\u00e0 s\u1ef1 ti\u1ebfn h\u00f3a li\u00ean t\u1ee5c c\u1ee7a n\u00f3. M\u1ed7i th\u1ebf h\u1ec7 nh\u00e2n \u0111\u00f4i t\u1ed1c \u0111\u1ed9 truy\u1ec1n d\u1eef li\u1ec7u so v\u1edbi th\u1ebf h\u1ec7 tr\u01b0\u1edbc, \u0111\u1ea3m b\u1ea3o kh\u1ea3 n\u0103ng t\u01b0\u01a1ng th\u00edch v\u1edbi c\u00e1c \u1ee9ng d\u1ee5ng ng\u00e0y c\u00e0ng \u0111\u00f2i h\u1ecfi cao h\u01a1n:<\/p>\n\n\n\n

\n\n<\/colgroup>

Th\u1ebf H\u1ec7 PCIe<\/strong><\/p><\/th>

T\u1ed1c \u0110\u1ed9 Truy\u1ec1n D\u1eef Li\u1ec7u (tr\u00ean m\u1ed7i \u0111\u01b0\u1eddng d\u1eabn)<\/strong><\/p><\/th>

B\u0103ng Th\u00f4ng (khe c\u1eafm x16)<\/strong><\/p><\/th>

N\u0103m Ph\u00e1t H\u00e0nh<\/strong><\/p><\/th><\/tr>

PCIe 3.0<\/strong><\/p><\/td>

8 GT\/s (~1 GB\/s tr\u00ean m\u1ed7i \u0111\u01b0\u1eddng d\u1eabn)<\/p><\/td>

~16 GB\/s<\/p><\/td>

2010<\/p><\/td><\/tr>

PCIe 4.0<\/strong><\/p><\/td>

16 GT\/s (~2 GB\/s tr\u00ean m\u1ed7i \u0111\u01b0\u1eddng d\u1eabn)<\/p><\/td>

~32 GB\/s<\/p><\/td>

2017<\/p><\/td><\/tr>

PCIe 5.0<\/strong><\/p><\/td>

32 GT\/s (~4 GB\/s tr\u00ean m\u1ed7i \u0111\u01b0\u1eddng d\u1eabn)<\/p><\/td>

~64 GB\/s<\/p><\/td>

2019<\/p><\/td><\/tr>

PCIe 6.0<\/strong><\/p><\/td>

64 GT\/s v\u1edbi PAM4 + FEC<\/p><\/td>

~128 GB\/s<\/p><\/td>

2022<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n

Kh\u1ea3 n\u0103ng t\u01b0\u01a1ng th\u00edch ng\u01b0\u1ee3c \u0111\u1ea3m b\u1ea3o r\u1eb1ng m\u1ed9t card PCIe 4.0 c\u00f3 th\u1ec3 ho\u1ea1t \u0111\u1ed9ng trong khe c\u1eafm PCIe 3.0, d\u00f9 hi\u1ec7u n\u0103ng s\u1ebd b\u1ecb gi\u1edbi h\u1ea1n \u1edf m\u1ee9c ti\u00eau chu\u1ea9n th\u1ea5p h\u01a1n.<\/p><\/blockquote>\n\n\n\n

\u27a3 <\/strong>V\u00ec Sao PCIe Quan Tr\u1ecdng?<\/h2>\n\n\n\n

\u0110\u01a1n V\u1ecb X\u1eed L\u00fd \u0110\u1ed3 H\u1ecda (GPU)<\/h3>\n\n\n\n

C\u00e1c GPU hi\u1ec7n \u0111\u1ea1i ph\u1ee5 thu\u1ed9c v\u00e0o k\u1ebft n\u1ed1i PCIe x16 \u0111\u1ec3 x\u1eed l\u00fd lu\u1ed3ng d\u1eef li\u1ec7u kh\u1ed5ng l\u1ed3 c\u1ea7n thi\u1ebft cho tr\u00f2 ch\u01a1i, hu\u1ea5n luy\u1ec7n tr\u00ed tu\u1ec7 nh\u00e2n t\u1ea1o v\u00e0 m\u00f4 ph\u1ecfng khoa h\u1ecdc.<\/p>\n\n\n\n

\u1ed4 \u1ee8ng D\u1ee5ng Giao Ti\u1ebfp NVMe (SSD)<\/h3>\n\n\n\n

Kh\u00e1c v\u1edbi c\u00e1c \u1ed5 SATA, NVMe<\/a> SSD s\u1eed d\u1ee5ng c\u00e1c \u0111\u01b0\u1eddng d\u1eabn PCIe \u0111\u1ec3 \u0111\u1ea1t t\u1ed1c \u0111\u1ed9 \u0111\u1ecdc\/ghi v\u01b0\u1ee3t qu\u00e1 7 GB\/s tr\u00ean PCIe 4.0, c\u1ea3i thi\u1ec7n \u0111\u00e1ng k\u1ec3 \u0111\u1ed9 ph\u1ea3n h\u1ed3i c\u1ee7a h\u1ec7 th\u1ed1ng.<\/p>\n\n\n\n

M\u1ea1ng M\u00e1y T\u00ednh v\u00e0 Trung T\u00e2m D\u1eef Li\u1ec7u<\/h3>\n\n\n\n

M\u00f4i tr\u01b0\u1eddng l\u01b0u tr\u1eef t\u1ed1c \u0111\u1ed9 cao b\u1ed9 \u0111i\u1ec1u khi\u1ec3n giao di\u1ec7n m\u1ea1ng (NIC)
<\/a>, b\u1ed9 gia t\u1ed1c FPGA v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n l\u01b0u tr\u1eef s\u1eed d\u1ee5ng PCIe \u0111\u1ec3 \u0111\u00e1p \u1ee9ng nhu c\u1ea7u \u0111i\u1ec7n to\u00e1n \u0111\u00e1m m\u00e2y v\u00e0 m\u00e1y ch\u1ee7 doanh nghi\u1ec7p.<\/p>\n\n\n\n

\u27a3 <\/strong>Ki\u1ebfn Tr\u00fac K\u1ef9 Thu\u1eadt<\/h2>\n\n\n\n

Giao th\u1ee9c PCIe \u0111\u01b0\u1ee3c chia th\u00e0nh ba l\u1edbp ch\u00ednh:<\/p>\n\n\n\n