{"id":4156,"date":"2025-11-05T11:12:00","date_gmt":"2025-11-05T11:12:00","guid":{"rendered":"https:\/\/lp.szlogic.cn\/glossary\/fpga-field-programmable-gate-array-explained\/"},"modified":"2026-06-22T08:59:27","modified_gmt":"2026-06-22T08:59:27","slug":"fpga-field-programmable-gate-array-explained","status":"publish","type":"post","link":"https:\/\/resourceslp.szlogic.cn\/ja\/glossary\/fpga-field-programmable-gate-array-explained","title":{"rendered":"FPGA\uff08\u30d5\u30a3\u30fc\u30eb\u30c9\u30d7\u30ed\u30b0\u30e9\u30de\u30d6\u30eb\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\uff09\u2014\u2014\u5b8c\u5168\u306a\u6280\u8853\u6982\u8981"},"content":{"rendered":"
\"What<\/figure>\n\n\n\n

FPGA\uff08\u30d5\u30a3\u30fc\u30eb\u30c9\u30d7\u30ed\u30b0\u30e9\u30de\u30d6\u30eb\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\uff09<\/strong> \u306f\u3001\u4e26\u5217\u30c7\u30b8\u30bf\u30eb\u8ad6\u7406\u51e6\u7406\u5411\u3051\u306b\u8a2d\u8a08\u3055\u308c\u305f\u518d\u69cb\u6210\u53ef\u80fd\u306a\u534a\u5c0e\u4f53\u30c7\u30d0\u30a4\u30b9\u3067\u3042\u308a\u3001 \u5de5\u7a0b\u5f8c\u306b\u3082\u30a8\u30f3\u30b8\u30cb\u30a2\u304c\u30ab\u30b9\u30bf\u30e0\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u6a5f\u80fd\u3092\u5b9f\u88c5\u3067\u304d\u308b\u3088\u3046\u306b\u3057\u307e\u3059\u3002\u4e00\u65b9\u3001<\/strong>, \u56fa\u5b9a\u547d\u4ee4\u30bb\u30c3\u30c8\u306b\u5f93\u3046 CPU\u3084GPU\u3068\u306f\u7570\u306a\u308a\u3001FPGA\u306e\u8ad6\u7406\u306fVerilog\u3084<\/a> VHDL\u306a\u3069\u306e\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u8a18\u8ff0\u8a00\u8a9e\uff08HDL\uff09\u3092\u7528\u3044\u3066\u69cb\u6210\u53ef\u80fd\u3067\u3059\u3002 Verilog<\/strong> \u307e\u305f\u306f VHDL<\/strong>.<\/p>\n\n\n\n

\u3053\u308c\u3089\u306f\u3001 5G\u901a\u4fe1\u3001\u9ad8\u901f\u30cd\u30c3\u30c8\u30ef\u30fc\u30ad\u30f3\u30b0\u3001\u822a\u7a7a\u96fb\u5b50\u6a5f\u5668\u3001\u7523\u696d\u30aa\u30fc\u30c8\u30e1\u30fc\u30b7\u30e7\u30f3\u3001\u30a8\u30c3\u30b8AI\u3001\u30ea\u30a2\u30eb\u30bf\u30a4\u30e0\u4fe1\u53f7\u51e6\u7406<\/strong>.<\/p>\n\n\n\n

\u25b6 FPGA\u3068\u306f\uff1f<\/h2>\n\n\n\n

FPGA\u3068\u306f\u3001 \u53ef\u5909\u69cb\u6210\u30ed\u30b8\u30c3\u30af\u30d6\u30ed\u30c3\u30af\uff08CLB\uff09\u3001\u30d7\u30ed\u30b0\u30e9\u30de\u30d6\u30eb\u30a4\u30f3\u30bf\u30fc\u30b3\u30cd\u30af\u30c8\u3001I\/O\u30d6\u30ed\u30c3\u30af\u3001\u7d44\u307f\u8fbc\u307f\u30e1\u30e2\u30ea\u3001\u304a\u3088\u3073\u30aa\u30d7\u30b7\u30e7\u30f3\u306eDSP\u30b9\u30e9\u30a4\u30b9\u3084\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u30a2\u30af\u30bb\u30e9\u30ec\u30fc\u30bf\u3067\u69cb\u6210\u3055\u308c\u308b<\/strong> \u96c6\u7a4d\u56de\u8def\u3067\u3059\u3002\u30a8\u30f3\u30b8\u30cb\u30a2\u306f\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u306e\u52d5\u4f5c\u3092\u30d7\u30ed\u30b0\u30e9\u30e0\u3059\u308b\u3053\u3068\u3067\u3001 \u30d1\u30d5\u30a9\u30fc\u30de\u30f3\u30b9\u3001\u9045\u5ef6\u3001\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u3092\u6700\u9069\u5316\u3057\u305f\u30ab\u30b9\u30bf\u30e0\u30c7\u30b8\u30bf\u30eb\u56de\u8def\u3092\u5b9f\u73fe\u3067\u304d\u307e\u3059\u3002<\/strong> FPGA\uff1d\u7279\u5b9a\u30bf\u30b9\u30af\u5411\u3051\u306b\u66f8\u304d\u63db\u3048\u30fb\u6700\u9069\u5316\u53ef\u80fd\u306a\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u3002.<\/p>\n\n\n\n

\u8981\u3059\u308b\u306b\uff1a<\/p>\n\n\n\n

\n

\u25b6 FPGA\u306e\u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3\u3068\u4e3b\u8981\u69cb\u6210\u8981\u7d20.<\/strong><\/p>\n<\/blockquote>\n\n\n\n

\"FPGA\uff1aField-Programmable<\/figure>\n\n\n\n

FPGA\u306e\u30b3\u30a2\u69cb\u6210\u8981\u7d20<\/h2>\n\n\n\n

FPGA\u69cb\u6210\u8981\u7d20<\/h3>\n\n\n\n
\n\n<\/colgroup>

\u53ef\u5909\u69cb\u6210\u30ed\u30b8\u30c3\u30af\u30d6\u30ed\u30c3\u30af\uff08<\/p><\/th>

\u6a5f\u80fd<\/p><\/th><\/tr>

CLB\u8ad6\u7406\u95a2\u6570\u304a\u3088\u3073\u7b97\u8853\u6f14\u7b97\u3092\u5b9f\u88c5<\/strong>)<\/p><\/td>

\u30eb\u30c3\u30af\u30a2\u30c3\u30d7\u30c6\u30fc\u30d6\u30eb\uff08LUT\uff09<\/p><\/td><\/tr>

\u8ad6\u7406\u30b2\u30fc\u30c8\u304a\u3088\u3073\u7d44\u307f\u5408\u308f\u305b\u8ad6\u7406\u3092\u751f\u6210<\/p><\/td>

\u30d5\u30ea\u30c3\u30d7\u30d5\u30ed\u30c3\u30d7\uff0f\u30ec\u30b8\u30b9\u30bf<\/p><\/td><\/tr>

\u72b6\u614b\u306e\u4fdd\u6301\u304a\u3088\u3073\u30c7\u30fc\u30bf\u306e\u30d1\u30a4\u30d7\u30e9\u30a4\u30f3\u51e6\u7406<\/p><\/td>

\u30d7\u30ed\u30b0\u30e9\u30de\u30d6\u30eb\u30a4\u30f3\u30bf\u30fc\u30b3\u30cd\u30af\u30c8<\/p><\/td><\/tr>

\u30ed\u30b8\u30c3\u30af\u8981\u7d20\u3092\u67d4\u8edf\u306b\u63a5\u7d9a<\/p><\/td>

DSP\u30b9\u30e9\u30a4\u30b9<\/p><\/td><\/tr>

\u6570\u5b66\u6f14\u7b97\uff08\u4f8b\uff1aMAC\u3001FFT\uff09\u3092\u9ad8\u901f\u5316<\/p><\/td>

\u30d6\u30ed\u30c3\u30afRAM\uff08BRAM\uff09<\/p><\/td><\/tr>

\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\uff0f\u30c7\u30fc\u30bf\u7528\u306e\u30aa\u30f3\u30c1\u30c3\u30d7\u30e1\u30e2\u30ea<\/p><\/td>

\u30c8\u30e9\u30f3\u30b7\u30fc\u30d0\uff08SERDES\uff09<\/p><\/td><\/tr>

\u9ad8\u901f\u30b7\u30ea\u30a2\u30eb\u901a\u4fe1<\/p><\/td>

I\/O\u30d0\u30f3\u30af<\/p><\/td><\/tr>

Ethernet PHY\u306a\u3069\u306e\u5916\u90e8\u30b7\u30b9\u30c6\u30e0\u3068\u306e\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30fc\u30b9<\/p><\/td>

FPGA\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u306e\u4ed5\u7d44\u307f<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n

FPGA\u30d3\u30c3\u30c8\u30b9\u30c8\u30ea\u30fc\u30e0\u306f\u3001\u8ad6\u7406\u5408\u6210\u3001\u914d\u7f6e\u3001\u914d\u7dda\u30c4\u30fc\u30eb\u306b\u3088\u3063\u3066\u751f\u6210\u3055\u308c\u307e\u3059\u3002\u5178\u578b\u7684\u306a\u30ef\u30fc\u30af\u30d5\u30ed\u30fc\uff1a<\/h3>\n\n\n\n

\u30a2\u30eb\u30b4\u30ea\u30ba\u30e0\uff0f\u8ad6\u7406\u8a2d\u8a08 \u2192 HDL\uff0fRTL\u30b3\u30fc\u30c7\u30a3\u30f3\u30b0 \u2192 \u5408\u6210 \u2192 \u30d3\u30c3\u30c8\u30b9\u30c8\u30ea\u30fc\u30e0 \u2192 FPGA\u8a2d\u5b9a<\/p>\n\n\n\n

\u25b6 FPGA vs CPU vs GPU vs ASIC\n<\/code><\/pre>\n\n\n\n
FPGA<\/h2>\n\n\n\n
\"FPGA<\/figure>\n\n\n\n
\n\n<\/colgroup>
\u6a5f\u80fd<\/p><\/th>
\u30d7\u30ed\u30b0\u30e9\u30de\u30d3\u30ea\u30c6\u30a3<\/p><\/th>
CPU<\/a><\/p><\/th>
GPU<\/a><\/p><\/th>
ASIC\uff08\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u7279\u5316\u578b\u96c6\u7a4d\u56de\u8def\uff09<\/a><\/p><\/th><\/tr>
\u518d\u69cb\u6210\u53ef\u80fd\u306a\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2<\/p><\/td>
\u30bd\u30d5\u30c8\u30a6\u30a7\u30a2\u306e\u307f<\/p><\/td>
\u56fa\u5b9a\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2<\/p><\/td>
\u56fa\u5b9a\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2<\/p><\/td>
\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u7279\u5316\u578b<\/p><\/td><\/tr>
\u4e26\u5217\u51e6\u7406\u80fd\u529b<\/p><\/td>
\u975e\u5e38\u306b\u9ad8\u3044<\/p><\/td>
\u4e2d\u7a0b\u5ea6<\/p><\/td>
\u975e\u5e38\u306b\u9ad8\u3044<\/p><\/td>
\u6975\u3081\u3066\u4f4e\u3044<\/p><\/td><\/tr>
\u30ec\u30a4\u30c6\u30f3\u30b7<\/p><\/td>
\u5c0e\u5165\u307e\u3067\u306e\u671f\u9593<\/p><\/td>
\u4e2d\u7a0b\u5ea6<\/p><\/td>
\u4e2d\u7a0b\u5ea6<\/p><\/td>
\u6700\u4f4e<\/p><\/td><\/tr>
\u30a8\u30cd\u30eb\u30ae\u30fc\u52b9\u7387<\/p><\/td>
\u9ad8\u3044<\/p><\/td>
\u4e2d\u7a0b\u5ea6<\/p><\/td>
\u4e2d\u7a0b\u5ea6<\/p><\/td>
\u975e\u5e38\u306b\u9ad8\u3044<\/p><\/td><\/tr>
\u65e9\u3044<\/p><\/td>
\u9577\u3044<\/p><\/td>
\u9577\u3044<\/p><\/td>
\u9577\u3044<\/p><\/td>
\u30ea\u30a2\u30eb\u30bf\u30a4\u30e0\u8ad6\u7406\u51e6\u7406\u3001\u30cd\u30c3\u30c8\u30ef\u30fc\u30ad\u30f3\u30b0\u3001\u4fe1\u53f7\u51e6\u7406<\/p><\/td><\/tr>
\u4e3b\u306a\u9069\u7528\u30b1\u30fc\u30b9<\/p><\/td>
\u4e00\u822c\u30b3\u30f3\u30d4\u30e5\u30fc\u30c6\u30a3\u30f3\u30b0<\/p><\/td>
\u5927\u898f\u6a21AI\u3001\u30b0\u30e9\u30d5\u30a3\u30c3\u30af\u30b9<\/p><\/td>
\u5927\u91cf\u751f\u7523\u5411\u3051\u56fa\u5b9a\u6a5f\u80fd<\/p><\/td>
\u25b6 \u4e3b\u306aFPGA\u5fdc\u7528\u5206\u91ce<\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n
\n\n<\/tbody>\n<\/table>\n<\/figure>\n\n\n\n
\u901a\u4fe1\u304a\u3088\u30735G<\/h2>\n\n\n\n
\u51e6\u7406\uff08eCPRI\u3001O-RAN\uff09<\/h3>\n\n\n\n
\n<\/colgroup>
\u5fdc\u7528<\/p><\/th>
\u8981\u4ef6<\/p><\/th>
LINK-PP\u30bd\u30ea\u30e5\u30fc\u30b7\u30e7\u30f3<\/p><\/th><\/tr>
\u7523\u696d\u7528PLC\u30b3\u30f3\u30c8\u30ed\u30fc\u30e9<\/p><\/td>
\u5805\u7262\u306a\u30a4\u30fc\u30b5\u30cd\u30c3\u30c8<\/p><\/td>
\u7523\u696d\u7528\u30de\u30b0\u30b8\u30e3\u30c3\u30af<\/a><\/p><\/td><\/tr>
\u30a8\u30c3\u30b8AI\u304a\u3088\u3073\u30b9\u30de\u30fc\u30c8\u30d3\u30b8\u30e7\u30f3<\/p><\/td>
\u9ad8\u901f\u30c7\u30fc\u30bf\uff0bPoE<\/p><\/td>
PoE\u5bfe\u5fdcRJ45\u30de\u30b0\u30b8\u30e3\u30c3\u30af<\/a><\/p><\/td><\/tr>
\u96fb\u6c17\u901a\u4fe1\u304a\u3088\u3073\u30d9\u30fc\u30b9\u30d0\u30f3\u30c9\u30e6\u30cb\u30c3\u30c8<\/p><\/td>
EMI\u306b\u654f\u611f\u306a\u30a4\u30fc\u30b5\u30cd\u30c3\u30c8<\/p><\/td>
\u30b7\u30fc\u30eb\u30c9\u4ed8\u304dRJ45<\/a><\/p><\/td><\/tr>
\u7d44\u8fbc\u307f\u5236\u5fa1\u30d7\u30e9\u30c3\u30c8\u30d5\u30a9\u30fc\u30e0<\/p><\/td>
\u30b3\u30f3\u30d1\u30af\u30c8\u3067\u7d71\u5408\u3055\u308c\u305fI\uff0fO<\/p><\/td>
\u7d71\u5408\u30de\u30b0\u30b8\u30e3\u30c3\u30af<\/a><\/p><\/td><\/tr><\/tbody>\n<\/table>\n<\/figure>\n\n\n\n
\u25b6 \u7d50\u8ad6<\/h2>\n\n\n\n
FPGA\u306f\u3001\u30ab\u30b9\u30bf\u30e0\u6027\u30fb\u9ad8\u6027\u80fd\u30c7\u30b8\u30bf\u30eb\u30ed\u30b8\u30c3\u30af\u3092\u5b9f\u73fe\u3057\u3001\u512a\u308c\u305f\u4e26\u5217\u51e6\u7406\u80fd\u529b\u3001\u4f4e\u9045\u5ef6\u3001\u6c7a\u5b9a\u8ad6\u7684\u51e6\u7406\u3092\u63d0\u4f9b\u3059\u308b\u305f\u3081\u3001 \u96fb\u6c17\u901a\u4fe1\u3001\u7523\u696d\u30aa\u30fc\u30c8\u30e1\u30fc\u30b7\u30e7\u30f3\u3001AI\u30a8\u30c3\u30b8\u30b3\u30f3\u30d4\u30e5\u30fc\u30c6\u30a3\u30f3\u30b0\u3001\u304a\u3088\u3073\u9ad8\u6027\u80fd\u30cd\u30c3\u30c8\u30ef\u30fc\u30ad\u30f3\u30b0\u306b\u304a\u3044\u3066\u4e0d\u53ef\u6b20\u3067\u3059\u3002<\/strong>. \u4fe1\u983c\u6027\u306e\u9ad8\u3044\u30a4\u30fc\u30b5\u30cd\u30c3\u30c8\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30fc\u30b9\uff08\u4f8b\uff1a LINK-PP\u7d71\u5408RJ45\u30b8\u30e3\u30c3\u30af\uff09\u3068\u7d44\u307f\u5408\u308f\u305b\u305f\u5834\u5408\u3001<\/strong><\/a>, \u3001FPGA\u30b7\u30b9\u30c6\u30e0\u306f\u5805\u7262\u306a\u63a5\u7d9a\u6027\u3001\u512a\u308c\u305fEMI\u6027\u80fd\u3001\u304a\u3088\u3073\u30b3\u30f3\u30d1\u30af\u30c8\u3067\u52b9\u7387\u7684\u306a\u5c55\u958b\u306e\u305f\u3081\u306e\u30aa\u30d7\u30b7\u30e7\u30f3PoE\u5bfe\u5fdc\u3092\u5b9f\u73fe\u3057\u307e\u3059\u3002.<\/p>\n\n\n\n
\u25b6 \u3088\u304f\u3042\u308b\u3054\u8cea\u554f\uff08FAQ\uff09<\/h2>\n\n\n\n
FPGA\u306f <\/strong>CPU<\/strong><\/a>?<\/strong>
\u306f\u3044\u3002\u4e26\u5217\u30ea\u30a2\u30eb\u30bf\u30a4\u30e0\u30bf\u30b9\u30af\u306b\u304a\u3044\u3066\u306f\u3001FPGA\u304c\u6c7a\u5b9a\u8ad6\u7684\u304b\u3064\u4f4e\u9045\u5ef6\u306e\u5b9f\u884c\u3092\u63d0\u4f9b\u3057\u307e\u3059\u3002.<\/p>\n\n\n\n
FPGA\u306f <\/strong>GPU<\/strong><\/a>?<\/strong>
\u3059\u3079\u3066\u306e\u5834\u5408\u306b\u7f6e\u304d\u63db\u3048\u308b\u3053\u3068\u306f\u3067\u304d\u307e\u305b\u3093\u3002GPU\u306fAI\u5b66\u7fd2\u306b\u512a\u308c\u3066\u3044\u307e\u3059\u304c\u3001FPGA\u306f\u30a8\u30c3\u30b8\u63a8\u8ad6\u304a\u3088\u3073\u30ea\u30a2\u30eb\u30bf\u30a4\u30e0\u5236\u5fa1\u30ef\u30fc\u30af\u30ed\u30fc\u30c9\u306b\u9069\u3057\u3066\u3044\u307e\u3059\u3002.<\/p>\n\n\n\n
\u306a\u305c <\/strong>ASIC\uff08\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u7279\u5316\u578b\u96c6\u7a4d\u56de\u8def\uff09<\/strong><\/a>?<\/strong>
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FPGA\uff08\u30d5\u30a3\u30fc\u30eb\u30c9\u30d7\u30ed\u30b0\u30e9\u30de\u30d6\u30eb\u30b2\u30fc\u30c8\u30a2\u30ec\u30a4\uff09\u3068\u306f\u4f55\u304b\u3001FPGA\u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3\u306e\u52d5\u4f5c\u539f\u7406\u30015G\u3001AI\u3001\u7523\u696d\u7528\u30b7\u30b9\u30c6\u30e0\u306b\u304a\u3051\u308b\u4e3b\u8981\u306a\u5fdc\u7528\u5206\u91ce\u3001\u304a\u3088\u3073\u7d71\u5408\u578bRJ45 MagJack\u306e\u91cd\u8981\u6027\u306b\u3064\u3044\u3066\u5b66\u3073\u307e\u3057\u3087\u3046\u3002.<\/p>","protected":false},"author":1,"featured_media":4155,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[27],"tags":[22],"class_list":["post-4156","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-glossary","tag-integrated-rj45-connectors"],"blocksy_meta":[],"acf":[],"_links":{"self":[{"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/posts\/4156","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/comments?post=4156"}],"version-history":[{"count":7,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/posts\/4156\/revisions"}],"predecessor-version":[{"id":11338,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/posts\/4156\/revisions\/11338"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/media\/4155"}],"wp:attachment":[{"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/media?parent=4156"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/categories?post=4156"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/resourceslp.szlogic.cn\/ja\/wp-json\/wp\/v2\/tags?post=4156"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}